PLDI 2025
Mon 16 - Fri 20 June 2025 Seoul, South Korea

This program is tentative and subject to change.

Mon 16 Jun 2025 16:00 - 16:20 at Violet - AI and Accelerator Architecture + WIP Chair(s): Yongjun Park

The growing adoption of AI applications has led to an increased demand for deploying neural networks on diverse device platforms. However, even modest networks now require specialized hardware for efficient execution due to their rising computational cost. To address this, distributed execution across connected, resource-constrained devices is gaining importance. While prior work relies on empirical models or supports limited partitioning, we present ADaPS, a novel framework for distributing Convolutional Neural Networks (CNNs) inference workloads across heterogeneous
embedded devices. Our analytical model partitions the height and width dimensions of 4D tensors and explores layer fusion opportunities, accounting for compute, memory, and communication constraints. ADaPS efficiently explores the vast partitioning space using a tree-based hybrid optimization algorithm combining Alpha-Beta pruning and dynamic programming. Evaluations on multiple CNNs and device configurations show that ADaPS is able to improve inference latency by up to 1.2x on average while significantly reducing data transfers compared to state-of-the-art methods.

This program is tentative and subject to change.

Mon 16 Jun

Displayed time zone: Seoul change

15:40 - 17:20
AI and Accelerator Architecture + WIPLCTES at Violet
Chair(s): Yongjun Park Yonsei University
15:40
20m
Talk
SPARQ: An Accelerator Architecture for Large Language Models with Joint Sparsity and Quantization Techniques
LCTES
Seonggyu Choi Sungkyunkwan University, Hyungmin Cho Sungkyunkwan University
DOI
16:00
20m
Talk
ADaPS: Adaptive Data Partitioning to Parallelize CNN Inference on Resource-Constrained Hardware
LCTES
Jaume Mateu Cuadrat Seoul National University, Bernhard Egger Seoul National University
DOI
16:20
20m
Talk
Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation
LCTES
Xinmiao Zhang SKLP, Institute of Computing Technology, CAS, Zheng Feng Institute of Computing Technology at Chinese Academy of Sciences, Shengwen Liang SKLP, Institute of Computing Technology, CAS, Xinyu Chen Hong Kong University of Science and Technology, Lei Zhang ICT CAS, Cheng Liu ICT CAS
DOI
16:40
20m
Talk
Modeling and Verification of Sigma Delta Neural Networks using Satisfiability Modulo Theory
LCTES
Sirshendu Das Indian Statistical Institute, Ansuman Banerjee Indian Statistical Institute, Swarup Kumar Mohalik Ericsson Research
DOI
17:00
10m
Talk
Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
LCTES
Siyi Xu Shanghai University, Limin Jiang Shanghai University, Yintao Liu Shanghai University, Yihao Shen Shanghai University, Yi Shi Shanghai University, Shan Cao Shanghai University, Zhiyuan Jiang Shanghai University
DOI
17:10
10m
Talk
Towards Macro-Aware C-to-Rust Transpilation (WIP)
LCTES
Robbe De Greef Vrije Universiteit Brussel, Attilio Discepoli Vrije Universiteit Brussel, Esteban Aguililla Klein Université Libre de Bruxelles, Théo Engels Royal Military Academy of Belgium, Ken Hasselmann Royal Military Academy of Belgium, Antonio Paolillo Vrije Universiteit Brussel
DOI
Hide past events