High-Level Synthesis (HLS) tools have greatly boosted hardware development productivity in the past decades, but still have a fundamental limitation: HLS is powerful in designing accelerators, not architectures – each individual design will be synthesized into independent hardware, and any possible hardware sharing must be done manually and explicitly.This is especially a problem when applied to rapidly evolving and diverse ML models, which significantly limits the practicality of HLS.

To address this limitation, we propose a novel framework to automatically identify the shared hardware modules among an input set of HLS programs. The framework leverages pattern anti-unification with e-graph exploration to identify the shared hardware. These hardware modules form the foundation of an accelerator architecture, balancing between the optimality for dedicated accelerators and the flexibility to handle diverse workloads. We automatically identify common modules over various datapaths, including fundamental ML operators such as Matrix Multiplication. Our framework can achieve up to a 46.1% reduction in the total area of hardware executing a group of designs.