PLDI 2025
Mon 16 - Fri 20 June 2025 Seoul, South Korea

This program is tentative and subject to change.

Thu 19 Jun 2025 14:40 - 15:00 at Grand Ball Room 2 - Architecture

When designing new architectural security mechanisms, a key question is whether they actually provide the intended security, but this has historically been very hard to assess. One cannot gain much confidence by testing, as such mechanisms should provide protection in the presence of arbitrary unknown code. Previously, one also could not gain confidence by mechanised proof, as the scale of production instruction-set architecture (ISA) designs, many tens or hundreds of thousands of lines of specification, made that prohibitive.

We focus in this paper especially on the secure encapsulation of software components, as supported by CHERI architectures in general and by the Arm Morello prototype architecture and hardware design in particular. Secure encapsulation is an essential security mechanism, for fault isolation and to constrain untrusted third-party code. It has previously often been implemented using virtual memory, but that does not scale to large numbers of compartments. Morello provides capability-based mechanisms that do scale, within a single address space.

We prove a strong secure encapsulation property for an example of encapsulated code running on Morello, that holds in the presence of arbitrary untrusted code, above a full-scale sequential model of the Morello ISA. To do so, we build on, extend, and unify three orthogonal lines of previous work: the Cerise proof of such an encapsulation property for a highly idealised capability machine, expressed using a logical relation in Iris; the Islaris approach for reasoning about known code in production-scale ISAs; and the T-CHERI security properties of arbitrary Morello code, previously proved only for executions up to domain crossing.

This demonstrates how one can prove such strong properties of security mechanisms for full-scale industry architectures.

This program is tentative and subject to change.

Thu 19 Jun

Displayed time zone: Seoul change

14:00 - 15:00
14:00
20m
Talk
Ripple: Asynchronous Programming for Spatial Dataflow Architectures
PLDI Research Papers
Souradip Ghosh Carnegie Mellon University, Yufei Shi Carnegie Mellon University, Brandon Lucia Carnegie Mellon University, Nathan Beckmann Carnegie Mellon University
DOI
14:20
20m
Talk
Making Concurrent Hardware Verification Sequential
PLDI Research Papers
Thomas Bourgeat EPFL, Jiazheng Liu Massachusetts Institute of Technology, Adam Chlipala Massachusetts Institute of Technology, Arvind Massachusetts Institute of Technology
DOI
14:40
20m
Talk
Morello-Cerise: A Proof of Strong Encapsulation for the Arm Morello Capability Hardware Architecture
PLDI Research Papers
Angus Hammond University of Cambridge, Ricardo Almeida University of Glasgow, Thomas Bauereiss University of Cambridge, Brian Campbell University of Edinburgh, Ian Stark University of Edinburgh, Peter Sewell University of Cambridge
DOI